AS4C256M16D4A-75BCN

AS4C256M16D4A-75BCN is a 256M x 16bit DDR4 synchronous DRAM (SDRAM). The DDR4 SDRAM is a high-speed dynamic random-access memory internally organized with eight banks (2 bank groups each with 4 banks). It uses an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operations to the DDR4 SDRAM are burst-oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an activate command, which is then followed by a read or write command.

• JEDEC standard compliant, supports JEDEC clock jitter specification, 1333MHz max clock
• Bidirectional differential data strobe, DQS and DQS#, differential clock, CK and CK#
• 8 internal banks: 2 groups of 4 banks each, separated IO gating structures by bank group
• 8n-bit prefetch architecture, precharge and active power down, boundary scan mode
• Auto refresh and self refresh, low-power auto self refresh (LPASR), read preamble training
• Self-refresh abort, fine granularity refresh, write levelling, DQ training via MPR
• Per DRAM addressability (PDA), output driver impedance control, dynamic on-die termination (ODT)
• Command/address latency (CAL), asynchronous reset, DLL enable/disable, ZQ calibration
• CAS latency (CL), CAS write latency (CWL), additive latency (AL): 0, CL-1, CL-2
• 96-ball FBGA package, commercial (extended) temperature range from 0°C to 95°C