AS4C16M32MD1-5BCN

AS4C16M32MD1-5BCN is a 512M (16M x32 bit) mobile DDR SDRAM. It is a 536,870,912 bits synchronous double data rate Dynamic RAM. Each 134,217,728bits bank is organized as 8,192 rows by 1024 columns by 16 bits or 8,192 rows by 512 columns by 32bits, fabricated with Alliance Memory’s high-performance CMOS technology. This device uses double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.

• Power supply : VDD, VDDQ = 1.7 to 1.95V, 200MHz (max.) clock frequency
• Four internal banks for concurrent operation, LVCMOS interface
• CAS# latency (CL) : 3, precharge : auto precharge option for each burst access
• Normal, 1/2, 1/4, 1/8 driver strength, auto-refresh, self-refresh, 8192cycles/64ms refresh cycles
• Low power consumption, partial array self-refresh (PASR), DDL is not implemented
• Double-data-rate architecture :two data transfers per one clock cycle
• The high-speed data transfer is realized by the 2bits prefetch pipelined architecture
• Bi-directional data strobe (DQS) is transmitted/received with data for capturing data at receiver
• Differential clock inputs (CK and CK#), data mask (DM) for write data
• 90-ball FBGA package, commercial (extended) temperature range from -25°C to 85°C