AS4C16M16MD1-6BCNTR

This AS4C16M16D1 is 268,435,456 bits synchronous double data rate Dynamic RAM. Each 67,108,864 bits bank is organized as 8,192 rows by 512 columns by 16 bits, fabricated with Alliance Memory's high performance CMOS technology. This device uses a double data rate architecture to achieve high- speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.

• CAS Latency: 2 and 3 VDD/VDDQ = 1.7~1.95V
• Burst Length: 2, 4, 8 and 16
• Data width: x16
• Burst Type: Sequential or Interleave
• Clock rate: 200MHz,166MHz , 133MHz
• 64 ms Refresh period
• Partial Array Self-Refresh(PASR)
• Interface: LVCMOS
• Auto Temperature Compensated Self-Refresh(ATCSR)
• Operating Temperature Range
• Power Down Mode Extended (-25? to + 85 ?)
• Deep Power Down Mode (DPD Mode) Industrial (-40? to + 85 ?)
• Programmable output buffer driver strength
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• Clock Stop capability during idle periods
• Auto Pre-charge option for each burst access
• Double data rate for data output
• Differential clock inputs (CK and CK )
• Bidirectional, data strobe (DQS)
• CAS Latency: 2 and 3
• Burst Length: 2, 4, 8 and 16
• Burst Type: Sequential or Interleave