These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic.All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse.Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
'174, 'LS174, 'S174 Contain Six Flip-Flops with Single-Rail Outputs
'175, 'LS175, 'S175 Contain Four Flip-Flops with Double-Rail Outputs
Three Performance Ranges Offered: See Table Lower Right