The 74ACT11286 universal 9-bit parity generator/checker features a local output for parity checking and a bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by cascading.
The XMIT\ control input is implemented specifically to accommodate cascading. When the XMIT\ is low, the parity tree is disabled and the PARITY ERROR output remains at a high logic level, regardless of the input levels. When XMIT\ is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.
The I/O control circuitry is designed so that the I/O port remains in the high-impedance state during power up or power down, to prevent bus glitches.
The 74ACT11286 is characterized for operation from -40°C to 85°C.
Inputs Are TTL-Voltage Compatible
Generates Either Odd or Even Parity for Nine Data Lines
Cascadable for n-Bits Parity
Center-Pin VCC and GND Configurations MinimizeHigh-Speed Switching Noise
EPICTM (Enhanced-Performance Implanted CMOS) 1-µm Process