From Assistive Tool to Real-Time Collaborator: AI Ultrasound Ushers in a New Era of Edge Intelligence

The design logic of ultrasound systems is undergoing a quiet transformation. For the past two decades, the central architectural question has been: “How can data captured by the probe be transferred to the back-end processing unit more quickly?” Today, however, a growing number of developers are asking a different question: Why must all of the data be transferred at all?

Behind this question lies an inevitable shift in ultrasound AI from cloud-based assistance to real-time processing at the edge. As AI evolves from a post-scan analysis tool into an active participant in real-time scan guidance, image quality assessment, and even preliminary lesion detection, the latency and bandwidth associated with data movement are no longer back-end metrics. They become hard constraints that directly shape the user and clinical experience.
 

PCIe Switches: Dynamic Routing for Multi-Source Data Across Boards

Traditional ultrasound systems are typically deployed in layers. The front-end analog front end (AFE) and beamforming FPGA are generally connected through high-speed serial links such as LVDS or JESD204B/C, either across separate boards or within the same board. The front-end acquisition and processing module is then connected to the back-end CPU/GPU through PCIe, Serial RapidIO (SRIO), Ethernet, or a high-speed backplane. As channel counts and sampling rates increase and AI inference modules are integrated, several issues become increasingly apparent: multiple data sources compete for the same path, latency becomes unpredictable, and bandwidth becomes a hard constraint.

A PCIe switch essentially provides a scalable, low-latency, high-bandwidth “expressway” for heterogeneous, multi-source data that must move across boards and accelerator domains. It is not intended to serve as the only pathway for every data stream.

In a new-generation ultrasound platform, probe signals are converted by an ADC and first undergo channel-level preprocessing in an acquisition FPGA or adaptive SoC. Only data-plane information that must move across boards, such as post-beamforming image frames, abstracted features, and down-sampled metadata, is dynamically routed through the PCIe switch to a back-end accelerator card. Different levels of AI processing operate at different points in the data chain.
 

• Raw-domain AI, such as channel-quality monitoring and adaptive beam-parameter adjustment, can process pre-beamform raw RF data directly. Because these tasks are extremely latency-sensitive, edge processing must be completed in the front-end FPGA or SoC.
• Image-domain AI, including segmentation, detection, and classification, must wait until the FPGA completes beamforming and generates image frames. The frames are then sent through the PCIe switch to an NPU, GPU, or the AI engine of an adaptive SoC for real-time inference.
• Control information, such as system logs and device status, can receive independent quality-of-service protection through PCIe traffic classes and related mechanisms, preventing it from competing with the data plane for bandwidth on critical paths.

The core value of this architecture is not simply greater speed, but distribution on demand. Different types of data follow different paths, while tasks with different priorities receive different resource guarantees. Physical-layer arbitration and contention associated with shared-bus architectures are reduced, and bandwidth competition is consolidated into manageable allocation within the switching fabric, significantly lowering end-to-end latency.

At the system level, PCIe switches support multi-device topologies and routing reconfiguration, leaving room for modular expansion. When a next-generation probe interface card or AI accelerator card is added, the system does not require a redesigned backplane; the routing table only needs to be reconfigured at the switch layer.
 

Heterogeneous Computing and On-Chip Data Localization: Bringing Inference Closer to the Source

Historically, ultrasound data flowed in a waterfall pattern: from the probe to the front-end FPGA, and then to the back-end CPU/GPU, with data repeatedly moved from one layer to the next. Today, however, AI models are being embedded into the imaging pipeline, requiring preliminary inference during beamforming, image reconstruction, or even at the probe. This means data must be retained and processed closer to its source.

This requires heterogeneous computing capabilities and hardware support for data localization. For example, dedicated AI accelerator cores or DSP cores can be integrated into an FPGA or SoC, allowing part of the AI inference workload to be completed locally without traversing the PCIe bus. This architecture not only reduces latency but also significantly lowers the power consumed by cross-chip data movement.

AMD, an Avnet partner, provides a relevant hardware foundation for heterogeneous computing with its second-generation Versal™ adaptive SoCs. In the second-generation Versal AI Edge series, for example, scalar performance in the processing system can increase by up to 10 times compared with the previous generation, with support for DDR5 and LPDDR5X memory. The new AI Engines introduce support for additional data types and can deliver up to three times higher energy efficiency, measured in TOPS per watt, than the previous generation. By integrating AI Engines, programmable logic, Arm multicore processors, and a second-generation network-on-chip (NoC2), the platform is well suited for advanced beamforming algorithms, image reconstruction, and other high-performance functions.


 

AI-Driven Dynamic Data Compression and Selective Transmission

Ultrasound imaging can generate hundreds of megabytes to tens of gigabytes of raw radio-frequency (RF) data every second. Uploading all of this data to an AI engine creates enormous bandwidth pressure and introduces unnecessary latency. Another important advance in AI-enabled healthcare is therefore to let AI participate in decisions about what to compress and what to transmit.

In ultrasound systems, conventional lossless or near-lossless compression, RF compression based on sparse representation or eigen-decomposition, and image/video codecs such as JPEG, H.264, and HEVC generally lack awareness of clinical semantics. They cannot directly distinguish the diagnostic value of different regions. Semantic-aware compression is therefore emerging as an important direction for next-generation ultrasound systems. An AI model intervenes in the post-beamforming image domain, identifies areas containing diagnostic information, such as blood-flow signals and tissue boundaries, and applies lossless or near-lossless processing to those areas while using higher compression ratios elsewhere. This selective-transmission strategy can substantially reduce the amount of transmitted data without compromising diagnostic quality.

The system can go further by dynamically adjusting its compression strategy according to the clinical scenario. In cardiac ultrasound, for example, AI can identify key frames in the cardiac cycle, such as end-diastolic frames, and prioritize their transmission quality. In obstetric screening, the system can place greater emphasis on preserving the integrity of the fetal contour. This clinically semantic-driven approach to data management reflects the evolution of ultrasound systems from “data movers” into “intelligent information managers”.
 

Conclusion

As AI moves from cloud-based assistance to real-time participation at the edge, it is becoming genuinely embedded in clinical workflows and helping clinicians reduce cognitive burden. As edge AI continues to expand across ultrasound, endoscopy, wearable monitoring, and other applications, Avnet will continue working with ecosystem partners to advance AI from an assistive tool into an indispensable real-time collaborator, enabling high-quality healthcare resources to serve every patient more equitably and efficiently.