When AI Clusters Reach 1.6T: Look Beyond GPUs - IP&E Is the Data Center’s “Hidden Bus”

In the 2026 AI data center landscape, attention remains fixed on GPU counts, HBM bandwidth, and liquid-cooling PUE. Yet when racks are ready for deployment, schedules are often constrained not by compute silicon, but by the seemingly inconspicuous cables, connectors, and retimers along the GPU-to-NIC/SuperNIC-to-switch link.

As 800G deployment accelerates, 1.6T ports are beginning to appear on ToR and leaf switches, while per-lane rates advance toward 200G PAM4. This pushes board-level signal-integrity margins to their limits. Although optical interconnects are expected to gain ground over copper in the long term, current deployments still favor active electrical cables (AECs) within a rack and between adjacent racks, while pluggable optical modules dominate across rack rows. Co-packaged optics (CPO) and near-packaged optics (NPO) are also being validated more rapidly by leading vendors as next-generation options. In this environment, the ability to integrate the IP&E and optoelectronic interconnect ecosystems is what turns headline bandwidth into effective throughput.
 

AECs and Retimers: Performance Amplifiers for Short- and Medium-Reach Links

The continuing expansion of AI clusters is creating an increasingly serious physical-layer challenge. Distances between GPUs and NICs or switches are growing, while signaling has progressed from 56G PAM4 to 100G PAM4 and is now moving toward 200G PAM4. Under these conditions, attenuation in conventional passive copper cables rises sharply and effective transmission distance contracts significantly, making it difficult to meet the link-margin requirements of cross-node connections within a rack.

Short- and medium-reach interconnects are therefore shifting rapidly from passive to active architectures. Avnet’s 800G AEC solution, built on Marvell DSP/retimer technology, supports retiming, equalization, and compensation for high-speed PAM4 signals. This extends copper reach, improves link stability, and supports mainstream 800G interconnect form factors such as OSFP and QSFP-DD.
 

Pluggable Optical Modules and Optical Interconnects: The Bandwidth Corridor Across Rack Rows

AECs secure the short- and medium-reach domain within a rack and between adjacent racks, but AI clusters extend far beyond that boundary. Longer-distance links across rack rows, as well as uplinks from ToR switches to the spine layer, remain the primary domain of pluggable optical modules.

As 1.6T ports move toward broader adoption, however, optical-module architectures are diverging. At 1.6T, conventional DSP-based modules can reach power levels of 25 W or even 30 W, making thermal management a hard constraint in chassis design. Linear pluggable optics (LPO) reduce module power substantially by removing the module-side DSP/retimer and shifting equalization to the host SerDes. CPO places the optical engine close to the switch ASIC, further shortening the electrical channel and avoiding losses from long PCB traces. Both approaches aim to reduce power per bit and latency, but they also create stricter interoperability requirements, raise the performance threshold for host SerDes, and introduce more complex operations and calibration workflows.

Whichever path is selected, control and management inside the optical module face increasing demands. AI data centers often operate at bandwidth utilization above 80%, while a training rollback in a cluster with tens of thousands of accelerators can result in losses of several million yuan. This places extremely high demands on module reliability and maintainability. As speeds advance from 800G to 1.6T, MCU clock frequency, memory capacity, and communication-interface bandwidth must scale in parallel. Avnet partner NXP offers an optical-module control MCU with integrated I3C, dual Cortex-M33 cores operating at 150 MHz, and data rates of up to 12.5 Mbps in SDR mode, providing an efficient and reliable foundation for optical interconnects in AI data centers.
 

High-Speed Backplane Connectors: Signal Rails for Chassis Backplanes

As interconnects move to 112G PAM4 and evolve toward the 224G generation, signal-integrity bottlenecks extend from cabling into backplane connectors. When signals travel across PCB traces and reach the backplane connector, return loss caused by impedance discontinuities becomes one of the key factors limiting system bit-error rate (BER). At 1.6T port densities, contact pitch continues to shrink, making crosstalk and insertion-loss control increasingly difficult.

Together, these challenges make the backplane connector one of the most demanding technical checkpoints in high-speed AI-cluster interconnects. Avnet is translating its signal-integrity expertise into deployable solutions. For 112G PAM4, it is promoting Amphenol ExaMAX2 backplane connectors and working with Molex on the Impulse series for 112G applications. For the transition to 224G, Amphenol Paladin HD and Molex’s next-generation Inception series provide an upgrade path from 112G to 224G, supporting high-bandwidth, low-latency physical-layer connectivity for GPU clusters and switches.
 

Passive Components and Power Delivery: A Voltage-Stability Defense Against Transient Current

On the power-delivery side of the data center, AI processors operate under heavy and highly dynamic loads, with transient current slew rates (di/dt) reaching hundreds or even thousands of amperes per microsecond. Such extreme transients exceed the closed-loop response capability of power-management ICs (PMICs), allowing the core voltage to drop significantly before the feedback loop can respond. The GPU or TPU power-delivery network (PDN) therefore requires a nearby, multi-stage parallel architecture combining high-frequency MLCCs with high-capacity energy-storage capacitors. These local storage components release energy rapidly during transient events, bridging the PMIC response gap and keeping core voltage rails within tight tolerance limits.

Avnet supplies a broad range of passive components, including high-capacitance devices using new anode materials and polymer tantalum capacitors, to improve the power-delivery robustness of AI accelerator cards under high-current transients.

Compute silicon defines the performance ceiling, but IP&E determines whether the system can remain stable under extreme load. From AEC copper cables and LPO modules to backplane connectors and passive components, these seemingly peripheral supporting players form the actual foundation for data movement in the 1.6T era.

They may not occupy the center of a compute specification sheet, but they support every part of the path from chip to port. Avnet’s focus is to make each inch of that physical link practical, reliable, and deployable.