HD6417616SFV | Renesas Electronics 32位微控制器 | Avnet Asia Pacific

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HD6417616SFV

微控制器, 32位, 62.5 MHz, 8 KB, 208 引脚

HD6417616SFV | 32位微控制器 | Renesas Electronics
Renesas Electronics
制造商: Renesas Electronics
安富利制造商模型#: HD6417616SFV
RoHS 6 Compliant
NCNR

The SH7616 is a CMOS single-chip microcontroller that integrates a high-speed CPU core using an original Renesas architecture with supporting functions required for an Ethernet system.The CPU has a RISC (Reduced Instruction Set Computer) type instruction set. The CPU basically operates at a rate of one instruction per cycle, offering a great improvement in instruction execution speed. In addition, the 32-bit internal architecture provides improved data processing power, and DSP functions have also been enhanced with the implementation of extended Harvard architecture DSP data bus functions. With this CPU, it has become possible to assemble low-cost, high-performance/high-functionality systems even for applications such as real time control, which could not previously be handled by microcontrollers because of their high-speed processing requirements. The SH7616 also includes a maximum 4-kbyte cache, for greater CPU processing power when accessing external memory.The SH7616 is equipped with a media access controller (MAC) conforming to the IEEE802.3u standard, and an Ethernet controller that includes a media independent interface (MII) standard unit, enabling 10/100 Mbps LAN connection. Supporting functions necessary for system configuration are also provided, including RAM, timers, a serial communication interface with FIFO (SCIF), interrupt controller (INTC), and I/O ports.To improve the efficiency of frame transmission/reception, the processing power of the DMAC for the Ethernet controller is improved and the FIFO for the DMAC has 2 kbytes. A CAM match signal input function is provided for systems that require multiple MAC addresses. In serial I/O with three channels, one operates with the FIFO for better data processing power when connected to the codec.

技术参数

  • Original Renesas architecture
  • 32-bit internal architecture
  • General register machine
    • Sixteen 32-bit general registers
    • Six 32-bit control registers (including 3 added for DSP use)
    • Ten 32-bit system registers
  • RISC (Reduced Instruction Set Computer) type instruction set
    • Fixed 16-bit instruction length for improved code efficiency
    • Load-store architecture (basic operations are executed between registers)
    • Delayed branch instructions reduce pipeline disruption during branches
    • C-oriented instruction set
  • Instruction execution time: One instruction per cycle (16.0 ns/instruction at 62.5 MHz operation)
  • Address space: Architecture supports 4 Gbytes
  • On-chip multiplier: Multiply operations (32 bits × 32 bits → 64 bits) and multiply-and-accumulate operations (32 bits × 32 bits + 64 bits → 64 bits) executed in two to four cycles
  • Five-stage pipeline

技术特性

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描述
最高工作温度 75 °C
集成电路安装 Surface Mount
最低工作温度 -20 °C
输入/输出数 29
集成电路外壳/封装 LQFP
最大电源电压 3.6, 5.5
引脚数 208
接口类型 H-UDI/SCIF
产品范围 SuperH Family SH7600 Series SH7616 Group Microcontrollers
MCU系列 SH7600
MCU系列 SuperH
最大工作频率 62.5
数据总线宽度 32 Bit

ECCN / UNSPSC

描述
ECCN: EAR99
计划交货期 B: 8542310000
HTSN: 8542310001

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标题 下载 类别 发布日期
REN2-RNCC-N-A0002299880-1 PCN EOL-Documentation 20160109
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