74HC4017PW,118

The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded outputs (Q0 to Q9), an output from the most significant flip-flop, two clock inputs and an overriding asynchronous master reset input. The counter is advanced by either a LOW-to-HIGH transition at Clock Input while Clock Input is LOW or a HIGH-to-LOW transition at Clock Input while CP0 is HIGH. When cascading counters, the output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero independent of the clock inputs. Automatic code correction of the counter is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.