XC9572XL-10VQ64C | AMD CPLD | Avnet Asia Pacific

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XC9572XL-10VQ64C

CPLD XC9500XL Family 1.6K Gates 72 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 64-Pin VTQFP

XC9572XL-10VQ64C | CPLD | AMD
AMD
制造商: AMD
产品分类: 可编辑逻辑, CPLD
安富利制造商模型#: XC9572XL-10VQ64C
RoHS 10 Compliant
NCNR
Obsolete

The FastFLASH XC9500XL family is a 3.3V CPLD family targeted for high-performance, low-voltage applications in leading-edge communications and computing systems, where high device reliability and low power dissipation is important. Each XC9500XL device supports in-system programming (ISP) and the full IEEE Std 1149.1 (JTAG) boundary-scan, allowing superior debug and design iteration capability for small form-factor packages. The XC9500XL family is designed to work closely with the Xilinx® Virtex®, Spartan®-XL and XC4000XL FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-density general purpose logic. The XC9500XL family members are fully pin-compatible, allowing easy design migration across multiple density options in a given package footprint.
The XC9500XL architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. In-system programming throughout the full commercial operating range and a high programming endurance rating provide worry-free reconfigurations of system field upgrades. Extended data retention supports longer and more reliable system operating life.
Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. Each user pin is compatible with 5V, 3.3V, and 2.5V inputs, and the outputs may be configured for 3.3V or 2.5V operation. The XC9500XL device exhibits symmetric full 3.3V output voltage swing to allow balanced rise and fall times.

技术参数

  • Optimized for high-performance 3.3V systems
    • 5 ns pin-to-pin logic delays, with internal systemfrequency up to 208 MHz
    • Small footprint packages including VQFPs, TQFPsand CSPs (Chip Scale Package)
    • Pb-free available for all packages
    • Lower power operation
    • 5V tolerant I/O pins accept 5V, 3.3V, and 2.5Vsignals
    • 3.3V or 2.5V output capability
    • Advanced 0.35 micron feature size CMOSFastFLASH technology
  • Advanced system features
    • In-system programmable
    • Superior pin-locking and routability withFastCONNECT II switch matrix
    • Extra wide 54-input Function Blocks
    • Up to 90 product-terms per macrocell withindividual product-term allocation
    • Local clock inversion with three global and oneproduct-term clocks
    • Individual output enable per output pin with localinversion
    • Input hysteresis on all user and boundary-scan pininputs
    • Bus-hold circuitry on all user pin inputs
    • Supports hot-plugging capability
    • Full IEEE Std 1149.1 boundary-scan (JTAG)support on all devices
  • Four pin-compatible device densities
    • 36 to 288 macrocells, with 800 to 6400 usablegates
  • Fast concurrent programming
  • Slew rate control on individual outputs
  • Enhanced data security features
  • Excellent quality and reliability
    • 10,000 program/erase cycles endurance rating
    • 20 year data retention
  • Pin-compatible with 5V core XC9500 family in commonpackage footprints

技术特性

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描述
集成电路外壳/封装 VTQFP
最高工作温度 70
引脚数 64
用户输入/输出数量 52
集成电路安装 Surface Mount
速度等级 10

ECCN / UNSPSC

描述
ECCN: EAR99
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