MT47H32M16NF-25E IT:H

MT47H32M16NF-25E IT:H is a DDR2 SDRAM. It uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially for 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single READ or WRITE operation for the DDR2 SDRAM consists of a single 4n-bitwide, two-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. It has JEDEC-standard 1.8V I/O (SSTL_18-compatible) with differential data strobe (DQS, DQS#) option.

• Operating voltage range is 1.8V (VDD)
• 32Meg x 16 configuration, adjustable data-output drive strength
• Packaging style is 84-ball 8mm x 12.5mm FBGA
• Timing (cycle time) is 2.5ns at CL = 5 (DDR2-800)
• 4n-bit prefetch architecture
• Data rate is 800MT/s
• DLL to align DQ and DQS transitions with CK, programmable CAS latency (CL)
• Posted CAS additive latency (AL), WRITE latency = READ latency - 1?CK
• Adjustable data-output drive strength, 64ms, 8192-cycle refresh
• On-die termination (ODT), supports JEDEC clock jitter specification