MT46H32M32LFB5-5 IT:B

The 1Gb Mobile LPDDR die contained within this package is a high-speed CMOS, dynamic random access memory containing 1,073,741,824 bits. It is internally configured as a quad-bank DRAM. Each of the x16’s 268,435,456-bit banks is organized as 16,384 rows by 1024 columns by 16 bits. Each of the x32’s 268,435,456-bit banks is organized as 8192 rows by 1024 columns by 32 bits.

• Vdd/Vddq = 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR) architecture; 2 data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center aligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data—one mask per byte
• Programmable burst lengths (BL): 2, 4, 8, or 161
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• On-chip temperature sensor to control self refresh rate
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• STATUS READ REGISTER (SRR) supported2
• Selectable output drive strength
• Clock stop capability
• 64ms refresh