MT40A4G8NEA-062E:F

MT40A4G8NEA-062E:F is a TwinDie™ 1.2V DDR4 SDRAM. This is a high-speed, CMOS dynamic random access memory device internally configured as two 16-bank DDR4 SDRAM devices. Although each die is tested individually within the dual-die package, some TwinDie test results may vary from a like-die tested within a monolithic die package. The DDR4 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.

• 128Meg x 8 x 16 banks x 2 ranks
• Each rank has 4 groups of 4 internal banks for concurrent operation
• 3200MT/s data rate
• 0.625ns at CL = 22 (DDR4-3200) timing – cycle time
• VDD = VDDQ = 1.2V (1.14–1.26V)
• 1.2V VDDQ-terminated I/O
• 13.75ns tAA, 13.75ns tRCD and 13.75ns tRP
• 128K A[16:0] row address and 1K A[9:0] column address
• 78-ball FBGA package (7.5mm x 11mm x 1.2mm) Die Rev :F
• Operating temperature commercial range from (0°C = TC = 95°C)