MT40A1G16TB-062E:F

MT40A1G16TB-062E:F is a DDR4 SDRAM. The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

• On-die, internal, adjustable VREFDQ generation
• 1.2V pseudo open-drain I/O
• 16 internal bank (x4, x8): 4 groups of 4 bank each, 8 internal banks (x16): 2 groups of 4 bank each
• Programmable data strobe preambles, data strobe preamble training, per-DRAM addressability
• Command/address latency (CAL), multipurpose register READ and WRITE capability
• Low-power auto self refresh (LPASR), temperature controlled refresh (TCR)
• Data bus inversion for data bus, command/address parity, databus write cyclic redundancy check (CRC)
• JEDEC JESD-79-4 compliant, sPPR and hPPR capability
• 1 Gig x 16 configuration, 96-ball 7.5mm x 13.0mm FBGA package
• Commercial temperature range from 0 to 95°C