74AUP1G373GW-Q100H | Nexperia 鎖存器 | Avnet Asia Pacific

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74AUP1G373GW-Q100H

Latch Transparent 3-ST 1-CH D-Type 6-Pin TSSOP T/R

74AUP1G373GW-Q100H | 鎖存器 | Nexperia
Nexperia
製造商: Nexperia
產品分類: 邏輯積體電路, 鎖存器
替代料號: 74AUP1G373GW-Q100H
RoHS 10 Compliant

The 74AUP1G373-Q100 provides the single D-type transparent latch with 3-state output. While the latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is LOW, the latch stores the information that was present at the D-input one set-up time preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the latch is available at the (Q) output. When pin OE is HIGH, the output goes to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the latch. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

技術參數

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from ‑40 °C to +85 °C and from ‑40 °C to +125°C
  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V
    • HBM JESD22-A114F Class 3A. Exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation

技術屬性

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描述
最小電源電壓 800 mV
集成電路外殼/封裝 TSSOP
最大電源電壓 3.6 V
引腳數 6
最高工作溫度 125 °C
通道數 1
最低工作溫度 -40 °C
邏輯 IC 系列 AUP
鎖存器類型 Transparent
芯片輸出類型 Non-Inverting
元素數量 One
傳播時延 22.1 ns
輸出電流 4 mA

ECCN/UNSPSC

描述
ECCN: EAR99
計劃交貨期 B: 8542390000
HTSN: 8542390001
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