IS61LF204836B-7.5TQLI | ISSI SRAM | Avnet Asia Pacific

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IS61LF204836B-7.5TQLI

SRAM Chip Sync Quad 3.3V 72M-Bit 2M x 36 7.5ns 100-Pin TQFP

IS61LF204836B-7.5TQLI | SRAM | ISSI
ISSI
製造商: ISSI
產品分類: 記憶體, SRAM
替代料號: IS61LF204836B-7.5TQLI
RoHS 6 Compliant

The 72Mb product family features high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LF204836B is organized as 2,096,952 words by 36 bits. Fabricated advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE\) input combined with one or more individual byte write signals (BWx\). In addition, Global Write (GW\) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP\ (Address Status Processor) or ADSC\ \(Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV\ (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.

技術參數

  • Internal self-timed write cycle
  • Individual Byte Write Control and Global Write
  • Clock controlled, registered address, data and control
  • Burst sequence control using MODE input
  • Three chip enable option for simple depth expansion and address pipelining
  • Common data inputs and data outputs
  • Auto Power-down during deselect
  • Single cycle deselect
  • Snooze MODE for reduced-power standby
  • JTAG Boundary Scan for PBGA package
  • Power Supply:Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%)
  • JEDEC 100-Pin TQFP, 119-pin PBGA, and 165- pin PBGA packages
  • Lead-free available.

技術屬性

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描述
時鐘頻率最大值 117 MHz
存儲密度 72 Mbit
最低工作溫度 -40 °C
引腳數 100
集成電路外殼/封裝 TQFP
集成電路貼裝 Surface Mount
SRAM類型 SDR
最高工作溫度 85 °C
最小電源電壓 3.135 V
額定電源電壓 3.3 V
最大電源電壓 3.465 V

ECCN/UNSPSC

描述
ECCN: 3A991.b.2.a
計劃交貨期 B: PARTS...
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