製造商:
ISSI
IS43DR16640B-3DBLI
DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin TWBGA
替代料號:
IS43DR16640B-3DBLI
RoHS 6 Compliant
DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin TWBGA
技術參數
- Clock frequency up to 400MHz
- 8 internal banks for concurrent operation
- 4-bit prefetch architecture
- Programmable CAS Latency: 3, 4, 5, 6 and 7
- Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6
- Write Latency = Read Latency-1
- Programmable Burst Sequence: Sequential or Interleave
- Programmable Burst Length: 4 and 8
- Automatic and Controlled Precharge Command
- Power Down Mode
- Auto Refresh and Self Refresh
- Refresh Interval: 7.8 µs (8192 cycles/64 ms)
- ODT (On-Die Termination)
- Weak Strength Data-Output Driver Option
- Bidirectional differential Data Strobe (Singleended data-strobe is an optional feature)
- On-Chip DLL aligns DQ and DQs transitions with CK transitions
- DQS# can be disabled for single-ended data strobe
- Read Data Strobe supported (x8 only)
- Differential clock inputs CK and CK#
- VDD and VDDQ = 1.8V ± 0.1V
- PASR (Partial Array Self Refresh)
- SSTL_18 interface
- tRAS lockout supported
- Operating temperature:
- Commercial (TA = 0°C to 70°C ; TC = 0°C to 85°C)
- Industrial (TA = -40°C to 85°C; TC = -40°C to 95°C)
- Automotive, A1 (TA = -40°C to 85°C; TC = -40°C to 95°C)
- Automotive, A2 (TA = -40°C to 105°C; TC = -40°C to 105°C)
- Configuration:
- 128Mx8 (16M x 8 x 8 banks)
- 64Mx16 (8M x 16 x 8 banks)
- Package:
- 60-ball TW-BGA for x8
- 84-ball TW-BGA for x16
- Self-Refresh:
- Standard
- Low Power (L)
技術屬性
查找類似的料號|
|
描述 | 值 |
|---|---|---|
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存儲密度 | 1 Gbit |
|
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集成電路貼裝 | Surface Mount |
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引腳數 | 84 |
|
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最高工作溫度 | 85 °C |
|
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集成電路外殼/封裝 | TWBGA |
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額定電源電壓 | 1.8 V |
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時鐘頻率最大值 | 333 MHz |
|
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最低工作溫度 | -40 °C |
|
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DRAM類型 | DDR2 SDRAM |
ECCN/UNSPSC
| 描述 | 值 |
|---|---|
| ECCN: | EAR99 |
| 計劃交貨期 B: | PARTS... |
| HTSN: | PARTS... |