XC7K160T-2FFG676I | AMD FPGA | Avnet Asia Pacific

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XC7K160T-2FFG676I

FPGA Kintex-7 Family 162240 Cells 28nm Technology 1V 676-Pin BGA

XC7K160T-2FFG676I | FPGA | AMD
AMD
製造商: AMD
產品分類: 可編輯邏輯, FPGA
替代料號: XC7K160T-2FFG676I
規格書
XC7K160T-2FFG676I
RoHS 10 Compliant

Xilinx 7 series FPGAs comprise three new FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7 series FPGAs include:
  • Kintex-7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.
Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.

技術參數

  • Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory.
  • 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.
  • High-performance SelectIO technology with support for DDR3 interfaces up to 1,866 Mb/s.
  • High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to maximum rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.
  • A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.
  • DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering.
  • Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.
  • Integrated block for PCI Express (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.
  • Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.
  • Low-cost, wire-bond, lidless flip-chip, and high signal integrity flipchip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option.
  • Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology and 0.9V core voltage option for even lower power.

技術屬性

查找類似的料號
描述 值
集成電路貼裝 Surface Mount
集成電路外殼/封裝 BGA
最高工作溫度 100
引腳數 676
邏輯單元數量 162
速度等級 2
最低工作溫度 -40
用戶輸入/輸出數量 250

ECCN/UNSPSC

描述 值
ECCN: 3A991.d
計劃交貨期 B: PARTS...
HTSN: PARTS...

文件

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文檔

標題 下載 類別 發布日期
7 Series FPGAs Family Overview Product-Guides 20130331
Kintex-7 FPGA Product Brief Product-Guides 20130331
7 Series FPGAs Memory Resources Guide User-Guides 20130331
Selector-Guides
7 Series FPGAs Clocking Resources Guide User-Guides 20130331
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