XC3S1600E-4FGG320C | AMD FPGA | Avnet Asia Pacific

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XC3S1600E-4FGG320C

FPGA Spartan-3E Family 1.6M Gates 33192 Cells 572MHz 90nm (CMOS) Technology 1.2V 320-Pin F-BGA

XC3S1600E-4FGG320C | FPGA | AMD
AMD
製造商: AMD
產品分類: 可編輯邏輯, FPGA
替代料號: XC3S1600E-4FGG320C
RoHS 10 Compliant
NCNR
Obsolete

The Spartan®-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The five-member family offers densities ranging from 100,000 to 1.6 million system gates.

The Spartan-3E family builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. These Spartan-3E FPGA enhancements, combined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.

Because of their exceptionally low cost, Spartan-3E FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment.

The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.

技術參數

  • Very low cost, high-performance logic solution for high-volume, consumer-oriented applications
  • Proven advanced 90-nanometer process technology
  • Multi-voltage, multi-standard SelectIO™ interface pins
  • Up to 376 I/O pins or 156 differential signal pairs
  • LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards
  • 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
  • 622+ Mb/s data transfer rate per I/O
  • True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential I/O
  • Enhanced Double Data Rate (DDR) support
  • DDR SDRAM support up to 333 Mb/s
  • Abundant, flexible logic resources
  • Densities up to 33,192 logic cells, including optional shift register or distributed RAM support
  • Efficient wide multiplexers, wide logic
  • Fast look-ahead carry logic
  • Enhanced 18 x 18 multipliers with optional pipeline
  • IEEE 1149.1/1532 JTAG programming/debug port
  • Hierarchical SelectRAM™ memory architecture
  • Up to 648 Kbits of fast block RAM
  • Up to 231 Kbits of efficient distributed RAM
  • Up to eight Digital Clock Managers (DCMs)
  • Clock skew elimination (delay locked loop)
  • Frequency synthesis, multiplication, division
  • High-resolution phase shifting
  • Wide frequency range (5 MHz to over 300 MHz)
  • Eight global clocks plus eight additional clocks per each half of device, plus abundant low-skew routing
  • Configuration interface to industry-standard PROMs
  • Low-cost, space-saving SPI serial Flash PROM
  • x8 or x8/x16 parallel NOR Flash PROM
  • Low-cost Xilinx® Platform Flash with JTAG
  • Complete Xilinx ISE® and WebPACK™ software
  • MicroBlaze™ and PicoBlaze embedded processor cores
  • Fully compliant 32-/64-bit 33 MHz PCI support (66 MHz in some devices)
  • Low-cost QFP and BGA packaging options
  • Common footprints support easy density migration
  • Pb-free packaging options

技術屬性

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描述
最高工作溫度 85
用戶輸入/輸出數量 250
引腳數 320
集成電路外殼/封裝 FBGA
集成電路貼裝 Surface Mount
速度等級 4
邏輯單元數量 33

ECCN/UNSPSC

描述
ECCN: 3A991.d
計劃交貨期 B: PARTS...
HTSN: PARTS...

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