Manufacturer:
Alliance Memory
AS4C256M16D3LC-12BCN
DRAM, DDR3L, 4 Gbit, 256M x 16bit, 800 MHz, 96-Pin, FBGA
Avnet Manufacturer Part #:
AS4C256M16D3LC-12BCN
RoHS 6 Compliant
AS4C256M16D3LC-12BCN is a 256M x 16-bit DDR3L synchronous DRAM (SDRAM). The 4Gb double-data-rate-3 (DDR3L) DRAM is a double data rate architecture to achieve high-speed operation. It is internally configured as an eight-bank DRAM. The 4Gb chip is organized as 32Mbit x 16 I/Os x8 bank devices. This synchronous device achieves high-speed double-data-rate transfer rates of up to 1866Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pairs in a source-synchronous fashion.
Key Features
- JEDEC standard compliant, supports JEDEC clock jitter specification
- Power supplies: VDD and VDDQ=1.35V (1.283 to 1.45V), backward compatible to VDD and VDDQ=1.5±0.075V
- Fully synchronous operation, differential clock, CK and CK#
- Bidirectional differential data strobe, DQS & DQS#
- 8 internal banks for concurrent operation, 8n-bit prefetch architecture
- Pipelined internal architecture, precharge and active power down
- Programmable burst lengths: 4, 8, burst type: sequential/interleave
- Output driver impedance control, write levelling, ZQ calibration, auto refresh and self refresh
- Dynamic ODT (Rtt-Nom and Rtt-WR), 800MHz maximum clock
- 96-ball FBGA package, commercial temperature range from 0°C to 95°C
Technical Attributes
Find Similar Parts|
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Description | Value |
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Operating Temperature Min | 0 °C |
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Memory Density | 4 Gbit |
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Supply Voltage Nom | 1.35 V |
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No. of Pins | 96 |
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Clock Frequency Max | 800 MHz |
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Operating Temperature Max | 95 °C |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| ECCN: | EAR99 |