TC358860XBG(ES)
CMOS Digital Integrated Circuit 65-Pin FBGA
- RoHS 10 Compliant
- Tariff Charges
TC358860XBG converts an Embedded Display Port (eDPTM) video stream into an MIPI® DSI stream. There are four eDP main link lanes in TC358860XBG, they can toggle at either 1.62, 2.16, 2.7, 3.24, 4.32, or 5.4 Gbps/link to receive up to 17.28 Gbps (5.4 Gbps x 0.8 x 4) of video stream. The 4-data lanes dual link DSI Tx can transmit up to 8 Gbps (1 Gbps x 4 x 2) of video stream. For input video stream with bandwidth (BW) < 4 Gbps, TC358860XBG can output the video data either with a single DSI link or performs left-right line split to output the video data stream with dual DSI links. For input video stream with BW requirements between 4 Gbps and 8 Gbps, left-right line split and dual DSI links usage is necessary.
TC358860XBG provides a compression engine which compress video data with 2-to-1 ratio. This enables TC358860XBG to receive 4K @60fps video streams at eDP Rx, compress and send out to a dual DSI link 4K panel for display. A de-compress engine is expected in the DSI panel.
Host/eDPTx controls/configures TC358860XBG chip by using its AUX channel (I²C over AUX). TC358860XBG provides mail box register/command queue for host to control/configure/command DSI panels, too. After host writes to the command queue, TC358860XBG starts DSI “command packets” to communicate with the DSI panels.
Alternatively, an external I²C master can configure TC358860XBG via I²C bus. Command queue address can also be access via I²C bus, which means Host can use I²C to access command queue, which in turn, controls DSI panel parameters.
- TC358860XBG follows the following standards:
- MIPI Alliance Specification for Display Serial Interface (DSI) version 1.1
- MIPI Alliance Specification for D-PHY Version1.1
- VESA DisplayPort Standard version 1.2a
- VESA Embedded DisplayPort Standard version 1.4
- eDP Sink (Receiver)
- Bit Rate @ 1.62, 2.16, 2.7, 3.24, 4.32 or 5.4Gbps, Voltage Swing @0.2 to 1.2 V, Pre-EmphasisLevel @3.5dB
- There are four lanes available in eDP main Link, which can operate in 1-, 2
- or 4-lane configuration
- Support Single-Stream Transport (SST), not multi-Stream Transport (MST)
- Capable of Full and Fast Link Training
- AUX channel with nominal bit rate at 1 Mbps
- Video input data formats supported: RGB666 and RGB888
- Absolute maximum pixel rate is 600 Mpixel/s
- Support Alternate Scrambler Seed Reset (ASSR) is used for content protection, Does notsupport HDCP encryption
- System designer can c
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Surface Mount | ||
| -40 to 85 °C | ||
| 65 | ||
| 5 x 5 x 0.25 | ||
| Industrial | ||
| FBGA | ||
| CMOS Digital Integrated Circuit |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | null |
| ECCN: | EAR99 |
| HTSN: | null |
| Schedule B: | null |