DF2144AFA20V

This LSI comprise microcomputers (MCUs) built around the H8S/2000 CPU, employing Renesas Technology proprietary architecture, and equipped with supporting modules on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip supporting modules required for system configuration include a data transfer controller (DTC) bus master, ROM and RAM, a 16-bit free-running timer module (FRT), 8-bit timer module (TMR), watchdog timer module (WDT), two PWM timers (PWM and PWMX), serial communication interface (SCI), PS/2-compatible keyboard buffer controller, host interface (HIF), D/A converter (DAC), A/D converter (ADC), and I/O ports. An I2 C bus interface (IIC) can also be incorporated as an option. The on-chip ROM is either flash memory (F-ZTAT*) or mask ROM, with a capacity of 128, 96, or 64 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. Three operating modes, modes 1 to 3, are provided, and there is a choice of address space and single-chip mode or externally expanded modes.

• H8S family/H8S/2100 series CPU core
• On-chip data transfer controller (DTC)
• 16MB linear address space
• SCI, IrDA and I2C communication interface
• 16bit free-running timer, 8bit timer, watchdog timer and PWM timers