NB6N14SMNR2G
Clock / Data Fanout Buffer, 1:4 AnyLevel™ Input, LVDS, 3.3 V
NB6N14SMNR2G is a differential 1:4 clock or data receiver and will accept AnyLevel differential input signals: LVPECL, CML or LVDS. These signals will be translated to LVDS and four identical copies of clock or data will be distributed, operating up to 2.0GHz or 2.5Gb/s, respectively. As such, the NB6N14S is ideal for SONET, GigE, fibre channel, backplane and other clock or data distribution applications. The NB6N14S has a wide input common mode range from GND + 50mV to VCC - 50mV. Combined with the 50 internal termination resistors at the inputs, the NB6N14S is ideal for translating a variety of differential or single-ended Clock or Data signals to 350mV typical LVDS output levels.
- Maximum input clock frequency 2.0GHz
- Maximum input data rate 2.5Gb/s
- 1ps maximum RMS clock jitter
- Typically 10ps data dependent jitter
- 380ps typical propagation delay
- 120ps typical rise and fall times
- VREF_AC reference output
- TIA/EIA - 644 compliant
- Functionally compatible with existing 3.3V LVEL, LVEP, EP and SG devices
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Fanout Buffer, Translator | ||
| QFN-EP | ||
| 2000 MHz | ||
| 2 GHz | ||
| CML, LVCMOS, LVDS, LVPECL, LVTTL | ||
| 1 | ||
| 4 | ||
| 16 | ||
| 85 °C | ||
| -40 °C | ||
| LVDS | ||
| NB6N14S Series | ||
| 3.6 Vdc | ||
| 3 Vdc |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | null |
| ECCN: | EAR99 |
| HTSN: | 8542390001 |
| Schedule B: | 8542390000 |