NB3W1200LMNTXG

The NB3N1200K and NB3W1200L differential clock buffers areDB1200Z and DB1200ZL compliant and are designed to work inconjunction with a PCIe compliant source clock synthesizer to providepoint-to-point clocks to multiple agents. The device is capable ofdistributing the reference clocks for Intel® QuickPath Interconnect(Intel QPI), PCIe Gen1/Gen2/Gen3, SAS, SATA, and Intel ScalableMemory Interconnect (Intel SMI) applications. The VCO of thedevice is optimized to support 100 MHz and 133 MHz frequencyoperation. The NB3N1200K and NB3W1200L utilizepseudo-external feedback topology to achieve low input-to outputdelay variation. The NB3N1200K is configured with the HCSL buffertype, while the NB3W1200L is configured with the low-powerNMOS Push-Pull buffer type.

• 12 Differential Clock Output Pairs @ 0.7 V
• Low-Power NMOS Push-Pull Compatible Outputs for NB3W1200L
• Optimized 100 MHz and 133 MHz Operating Frequencies to MeetThe Next Generation PCIe Gen 2/Gen 3 and Intel QPI Phase Jitter
• DB1200ZL Compliant
• 3.3 V ±5% Supply Voltage Operation
• Fixed-Feedback for Lowest Input-To-Output Delay Variation
• SMBus Programmable Configurations to Allow Multiple Buffers in aSingle Control Network
• PLL Bypass Configurable for PLL or Fanout Operation
• Programmable PLL Bandwidth
• 2 Tri-level Addresses Selection (9 SMBUS Addresses)
• Individual OE Control Pin for Each of 12 Outputs
• Low Phase Jitter (Intel QPI, PCIe Gen 2/Gen 3 Phase Jitter Compliant)
• 50 ps Max Output-to-Output Skew Performance
• 50 ps Max Cycle-to-Cycle Jitter (PLL mode)
• 100 ps Input to Output Delay Variation Performance
• QFN 64-pin Package, 9 mm x 9 mm
• Spread Spectrum Compa