MC100LVEP14DTG
2.5 V / 3.3 V 1:5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer
The MC100LVEP14 is a low skew 1 to 5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions.
- 100 ps Device-to-Device Skew
- 25 ps Within Device Skew
- 400 ps Typical Propagation Delay
- Maximum Frequency > 2 GHz Typical
- PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V
- NECL Mode: VCC = 0 V with VEE = -2.375 V to -3.8 V
- LVDS Input Compatible
- Open Input Default State
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Clock Driver, Fanout Buffer | ||
| 2.5 GHz | ||
| 1 GHz | ||
| ECL, HSTL, LVECL, LVPECL, PECL | ||
| 2 | ||
| 5 | ||
| 20 | ||
| 85 °C | ||
| -40 °C | ||
| LVECL, LVPECL | ||
| MC100LVEP14 Series | ||
| 3.8 Vdc | ||
| 2.375 Vdc |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | null |
| ECCN: | EAR99 |
| HTSN: | 85423990 |
| Schedule B: | 85423990 |
Factory Lead Time: