74HC373PW-Q100,118

The 74HC373-Q100; 74HCT373-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A. The 74HC373-Q100; 74HCT373-Q100 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus-oriented applications. A latch enable (LE) input and an output enable input are common to all latches. The 74HC373-Q100; 74HCT373-Q100 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output changes state each time its corresponding D input changes. When LE is LOW, the latches store the information that was present at the D inputs a set-up time preceding the HIGH-to-LOW transition of LE. When output enable is LOW, the contents of the 8 latches are available at the outputs. When output enable is HIGH, the outputs go to the highimpedance OFF-state. Operation of the output enable input does not affect the state of the latches. The 74HC373-Q100; 74HCT373-Q100 is functionally identical to:

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
• Input levels:
  • For 74HC373-Q100: CMOS level
  • For 74HCT373-Q100: TTL level
• 3-state non-inverting outputs for bus-oriented applications
• Common 3-state output enable input
• Functionally identical to the 74HC573-Q100; 74HCT573-Q100
• ESD protection:
  • MIL-STD-883, method 3015 exceeds 2000 V
  • HBM JESD22-A114F exceeds 2000 V
  • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ?)
• Multiple package options