74ALVT16373DGG,118

74ALVT16373DGG,118 is a 16bit D-type transparent latch with 3-state outputs. This device can be used as two 8bit transparent latches or a single 16bit transparent latch. This device features two latch enables (1LE and 2LE) and two output enable (1 active-low OE and 2 active-low OE), each controlling 8bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on n active-low OE causes the outputs to assume a high-impedance OFF-state. Operation of the n active-low OE input does not affect the state of the latches. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs. It features ESD protection (MIL STD 883 method 3015: exceeds 2000V, MM exceeds 200V).

• Overvoltage tolerant inputs to 5.5V, BiCMOS high speed and output drive
• 16bit transparent latch, 5V I/O compatible, 3-state buffers
• Direct interface with TTL levels, input and output interface capability to systems at 5V supply
• Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
• Live insertion/extraction permitted, power-up reset, power-up 3-State
• No bus current loading when output is tied to 5V bus
• IOFF circuitry provides partial power-down mode operation
• Latch-up performance exceeds 500mA per JESD 78 Class II Level B
• Supply voltage range from 2.3 to 2.7V (VCC = 2.5V ±0.2V), 3 to 3.6V (VCC = 3.3V ±0.3V)
• Operating temperature range from -40°C to +85°C, TSSOP48 package