MT46H64M16LFBF-5 IT:B

MT46H64M16LFBF-5 IT:B is a mobile low-power DDR SDRAM. The 1Gb mobile low-power DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It is internally configured as a quad-bank DRAM. Each of the x16’s 268,435,456-bit banks is organized as 16,384 rows by 1024 columns by 16 bits. Each of the x32’s 268,435,456-bit banks is organized as 8192 rows by 1024 columns by 32 bits. The mobile LPDDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O.

• VDD/VDDQ = 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS), differential clock inputs (CK and CK#)
• Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
• Commands entered on each positive CK edge, 4 internal banks for concurrent operation
• DQS edge-aligned with data for READs; centre aligned with data for WRITEs
• Data masks (DM) for masking write data; one mask per byte, auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs, clock stop capability
• 64 Meg x 16 (16 Meg x 16 x 4 banks) configuration, JEDEC-standard addressing
• 60-ball VFBGA (8mm x 9mm) package, 5ns at CL = 3 (200MHz) timing – cycle time
• Industrial operating temperature range from -40°C to +85°C