MT41K128M16JT-107:K
DRAM, DDR3L, 2 Gbit, 128M x 16bit, 933 MHz, 96 Pins, FBGA
MT41K128M16JT-107:K is a DDR3L SDRAM that uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I
- 128 Meg x 16 configuration, tCK = 1.071ns, CL = 13 speed grade
- VDD = VDDQ = 1.35V (1.283 to 1.45V)
- Backward-compatible to VDD = VDDQ = 1.5V ±0.075V
- Differential bidirectional data strobe, 8n-bit prefetch architecture
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 17 Bit | ||
| 933 MHz | ||
| 16 Bit | ||
| 2 Gbit | ||
| DDR3L SDRAM | ||
| FBGA | ||
| Surface Mount | ||
| 1866 MHz | ||
| 156 mA | ||
| 128M x 16bit | ||
| 2 Gbit | ||
| Surface Mount | ||
| 96 | ||
| 16 Bit | ||
| 16 Bit | ||
| 1.35 V | ||
| 0 to 95 °C | ||
| 95 °C | ||
| 0 °C | ||
| 96F-BGA | ||
| 96 | ||
| 14 x 8 x 0.75 mm | ||
| Commercial | ||
| FBGA | ||
| 1.35 V | ||
| DDR3L SDRAM |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | null |
| ECCN: | EAR99 |
| HTSN: | PARTS... |
| Schedule B: | PARTS... |
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