IS45S16800F-6TLA1-TR

The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V Vdd and 3.3V Vddq memory systems containing 134,217,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is organized as 4,096 rows by 512 columns by 16 bits. The 128MbS DRAM includes an AUTOREFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTOPRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option.

• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a positive clock edge Organization 16Mx8
• Internal bank for hiding row access/precharge
• Power supply: Vdd 3.3V Vddq 3.3V
• LVTTL interface
• Programmable burst length -(1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 4096 refresh cycles every 16 ms (A2 grade) or 64 ms (A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Temperature Ranges: Automotive and A1 (-40°C to +85°C) Automotive, A2 (-40°C to +105°C)
• Package-54-pin TSOPII, 54-ball BGA.