IS25WP064A-JKLE

The IS25WP064A Serial Flash memory offers a versatile storage solution with high flexibility and performance in a simplified pin count package. Flash is for systems that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions). The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to 66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate) commands that transfer addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in place) operation. The memory array is organized into programmable pages of 256-bytes. This family supports page program mode where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface) supports 2- cycle instruction further reducing instruction times. Pages can be erased in groups of 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications requiring solid data retention.

• Industry Standard Serial Interface
  • IS25WP064: 64Mbit/8Mbyte
  • 256 bytes per Programmable Page
  • Supports standard SPI, Fast, Dual, DualI/O, Quad, Quad I/O, SPI DTR, Dual I/ODTR, Quad I/O DTR, and QPI Supports Serial Flash DiscoverableParameters (SFDP)
• High Performance Serial Flash (SPI)
  • 50MHz Normal and 133Mhz Fast Read
  • 532 MHz equivalent QPI
  • DTR (Dual Transfer Rate) up to 66MHz
  • Selectable Dummy Cycles
  • Configurable Drive Strength
  • Supports SPI Modes 0 and 3
  • More than 100,000 Erase/Program Cycles
  • More than 20-year Data Retention
• Flexible and Efficient Memory Architecture
  • Chip Erase with Uniform: Sector/BlockErase (4/32/64 Kbyte)
  • Program 1 to 256 Bytes per Page
  • Program/Erase Suspend and Resume
• Efficient Read and Program modes
  • Low Instruction Overhead Operations
  • Continuous Read 8/16/32/64-Byte BurstWrap