AS7C34098A-10TCN
SRAM Chip Async Single 3.3V 4M-Bit 256K x 16 10ns 44-Pin TSOP-II
- RoHS 10 Compliant
- Tariff Charges
AS7C34098A-10TCN is a high-performance CMOS 4,194,304-bit static random access memory (SRAM) device organized as 262,144 words × 16bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. A read cycle is accomplished by asserting output enable (active-low OE) and chip enable (active-low CE), with write enable (active-low WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. The device provides multiple centre power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. Active-low LB controls the lower bits, I/O1–I/O8, and active-low UB controls the higher bits, I/O9–I/O16.
- Pin compatible with AS7C34098
- Centre power and ground pins, high speed
- Low power consumption, 650mW/max at 10ns active, 28.8mW/max CMOS standby
- Individual byte read/write controls
- Easy memory expansion with active-low CE, active-low OE inputs
- TTL- and CMOS-compatible, three-state I/O
- ESD protection = 2000volts
- Latch-up current = 200mA
- 10ns access time, TSOP 2 package
- Commercial temperature range from 0°C to 70°C
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 18 Bit | ||
| 4 Mbit | ||
| TSOP-II | ||
| Surface Mount | ||
| 170 mA | ||
| 10 ns | ||
| 256K x 16bit | ||
| 4 Mbit | ||
| Surface Mount | ||
| 44 | ||
| 16 Bit | ||
| 16 Bit | ||
| 1 | ||
| 256 kWords | ||
| 0 to 70 °C | ||
| 70 °C | ||
| 0 °C | ||
| 44TSOP-II | ||
| 44 | ||
| 18.54 x 10.29 x 1.05 mm | ||
| No | ||
| Commercial | ||
| Asynchronous SRAM | ||
| TSOP-II | ||
| 3.6 V | ||
| 3 V | ||
| 3.3 V | ||
| Asynchronous | ||
| 3.3000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | null |
| ECCN: | 3A991.b.2.a |
| HTSN: | PARTS... |
| Schedule B: | PARTS... |