NCP51402MNTXG
3 Amp VTT Termination Regulator DDR1, DDR2, DDR3, LPDDR3, DDR4 No droop, 29deg phase margin. ONSSPCLDO;
The NCP51402 is a source/sink Double Data Rate (DDR) termination regulator specifically designed for low input voltage and low-noise systems where space is a key consideration. The NCP51402 maintains a fast transient response and only requires a minimum output capacitance of 20 F. The NCP51402 supports a remote sensing function and all power requirements for DDR VTT bus termination. The NCP51402 can also be used in low-power chipsets and graphics processor cores that require dynamically adjustable output voltages. The NCP51402 is available in the thermally-efficient DFN10 Exposed Pad package, and is rated both Green and Pb-free.
Input Voltage Rails: Supports 2.5 V, 3.3 V and 5 V Rails PVCC Voltage Range: 1.1 to 3.5 V Integrated Power MOSFETs Fast Load-Transient Response PGOOD - Logic output pin to Monitor VTT Regulation EN - Logic input pin for Shutdown mode VRI - Reference Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider Remote Sensing (VTTS) Built-in Under Voltage Lockout and Over Current Limit Thermal Shutdown Small, Low-Profile 10-pin, 3x3 DFN Package These Devices are Pb-Free and are RoHS Compliant
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| DDR1, DDR2, DDR3 | ||
| 10 | ||
| 125 °C | ||
| -40 °C | ||
| 750mV 3A LDO Voltage Regulators | ||
| 3 A | ||
| 5.5 V | ||
| 2.375 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | null |
| ECCN: | EAR99 |
| HTSN: | 8542390001 |
| Schedule B: | 8542390000 |