Inactivity Warning Dialog
SiP32429 is load switches that integrate multiple control features that simplify the design and increase the reliability of the circuitry connected to the switch. Both devices are 56 m switches designed to operate in the 6 V to 28 V range. An internally generated gate drive voltage ensures good RON linearity over the input voltage operating range.
The SiP32429 have a slew rate control circuit that controls the switch turn-on time to the value set by an external capacitor.
After soft start, an over-current protection circuit (OCP) continuously monitors the current through the load switch, and controls the switch impedance to limit the current to the level programmed by an external resistor. If the over-current condition persists for more than 7 ms, the switch shuts off automatically. The SiP32429 has an over temperature protection circuit (OTP) which will shut the switch off if the junction temperature exceeds about 135 °C. The OTP circuit will release the switch when the temperature has decreased by about 40 °C of hysteresis.
When an OCP or an OTP fault condition is detected the FLG pin is pulled low. For the SiP32429, the fault flag will release 150 ms after the fault condition is cleared, and the switch will automatically turn on at the programmed slew rate.
These devices feature a low voltage control logic interface which can be controlled without the need for level shifting. These devices also include a power good flag. SiP32419 and SiP32429 are available in a space efficient DFN10 3 mm x 3 mm package.
Key Features
|
Description | Value |
---|---|---|
|
IC Case / Package | DFN-EP |
|
Current Limit | 4.5 A |
|
On State Resistance | 72 mOhm |
|
No. of Pins | 10 |
|
Operating Temperature Min | -40 °C |
|
Input Voltage | 28 V |
|
No. of Outputs | 1 |
|
No. of Channels | 1 |
|
Operating Temperature Max | 85 °C |
|
Power Load Switch Type | High Side |
Description | Value |
---|---|
ECCN: | EAR99 |
SCHEDULE B: | 8542390000 |
HTSN: | 8542390001 |
Documents
Title | Download | Type | Date Published |
---|---|---|---|
Internal logic circuit reset delay time is adjusted during power off to be aligned with fault alert off. | PCN-Documentation | 20200406 |