DF71253D50FPV#Z1

CPU Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture (basic operations are executed between registers) Sixteen 32-bit general registers Five-stage pipeline On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits) executed in two to five cycles C language-oriented 62 basic instructions Operating modes Operating modes Single chip mode Operating states Program execution state Exception handling state Power-down modes Sleep mode Software standby mode Module standby mode User break controller (UBC) Addresses, data values, type of access, and data size can all be set as break conditions Supports a sequential break function Two break channels On-chip ROM : 128 kbytes On-chip ROM : 8 kbytes Interrupt controller (INTC) External interrupt pins : Five pins (NMI and IRQ3 to IRQ0) On-chip peripheral interrupts: Priority level set for each module Vector addresses: A vector address for each interrupt source User debugging interface (H-UDI) E10A emulator support Clock pulse generator (CPG) Clock mode: Input clock can be selected from external input or crystal resonator Four types of clocks generated: CPU clock: Maximum 50 MHz Bus clock: Maximum 40 MHz Peripheral clock: Maximum 40 MHz MTU2 clock: Maximum 40 MHz Watchdog timer (WDT) On-chip one-channel watchdog timer Interrupt generation is supported