74LVC1G74DP-Q100H by Nexperia Flip Flops | Avnet Asia Pacific

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74LVC1G74DP-Q100H

Flip Flop, 74LVC1G74, D, 4.1 ns, 280 MHz, 32 mA, 8 Pins, TSSOP

74LVC1G74DP-Q100H in Flip Flops by Nexperia
Nexperia
Manufacturer: Nexperia
Product Category: Logic ICs, Flip Flops
Avnet Manufacturer Part #: 74LVC1G74DP-Q100H
RoHS 10 Compliant

The 74LVC1G74-Q100 is a single positive edge triggered D-type flip-flop. It has individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Key Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 1.65 V to 5.5 V
  • 5 V tolerant inputs for interfacing with 5 V logic
  • High noise immunity
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8-B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • MIL-STD-883, method 3015 exceeds 2000 V
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • Inputs accept voltages up to 5 V
  • Multiple package options

Technical Attributes

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Description Value
Minimum Operating Supply Voltage 1.65 V
Supply Voltage Max 5.5 V
Operating Temperature Min -40 °C
Supply Voltage Min 1.65 V
No. of Channels 1
Logic IC Family 74LVC
Trigger Type Positive Edge
Frequency 280 MHz
IC Output Type Complementary
Logic Family / Base Number 74LVC1G74
Logic IC Base Number 741G74
Output Current 32 mA
No. of Elements One
Flip-Flop Type D
Propagation Delay 4.1 ns
IC Case / Package TSSOP
Qualification AEC-Q100
Operating Temperature Max 125 °C
No. of Pins 8

ECCN / UNSPSC / COO

Description Value
ECCN: EAR99
SCHEDULE B: 8542390000
HTSN: 8542390001
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