74HC595D,118

74HC595D,118 is an 8-bit serial-in, serial or parallel-out shift register with output latches 3-state. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset (active-low) MR input. A LOW on (active-low)MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (active-low) (OE) is LOW. A HIGH on (active-low) OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. Suitable for serial-to-parallel data conversion, remote control holding register applications.