MT47H32M16NF-25E AAT:H

MT47H32M16NF-25E AAT:H is a DDR2 SDRAM. It uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is for 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single READ or WRITE operation for the DDR2 SDRAM consists of a single 4n-bitwide, two-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. It has JEDEC-standard of 1.8V I/O (SSTL_18-compatible) and differential data strobe (DQS, DQS#) option.