XC4VSX55-10FFG1148C by AMD FPGAs | Avnet Asia Pacific

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XC4VSX55-10FFG1148C

FPGA Virtex-4 SX Family 55296 Cells 90nm (CMOS) Technology 1.2V 1148-Pin FC-BGA

XC4VSX55-10FFG1148C in FPGAs by AMD
AMD
Manufacturer: AMD
Product Category: Programmable Logic, FPGAs
Avnet Manufacturer Part #: XC4VSX55-10FFG1148C
RoHS 10 Exempt

Combining Advanced Silicon Modular Block (ASMBL) architecture with a wide variety of flexible features, the Virtex®-4 family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ASIC technology. Virtex-4 FPGAs comprise three platform families—LX, FX, and SX—offering multiple feature choices and combinations to address all complex applications. The wide array of Virtex-4 FPGA hard-IP core blocks includes the PowerPC® processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers, dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4 FPGA building blocks are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X product families, so previous-generation designs are upward compatible. Virtex-4 devices are produced on a state-of-the-art 90 nm copper process using 300 mm (12-inch) wafer technology.

Key Features

  • Virtex-4 SX: High-performance solution for digital signal processing (DSP) applications
  • Xesium™ Clock Technology
    • Digital clock manager (DCM) blocks
    • Additional phase-matched clock dividers (PMCD)
    • Differential global clocks
  • XtremeDSP™ Slice
    • 18 x 18, two’s complement, signed Multiplier
    • Optional pipeline stages
    • Built-in Accumulator (48-bit) and Adder/Subtracter
  • Smart RAM Memory Hierarchy
    • Distributed RAM
    • Dual-port 18-Kbit RAM blocks · Optional pipeline stages · Optional programmable FIFO logic automatically remaps RAM signals as FIFO signals
    • High-speed memory interface supports DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.
  • SelectIO™ Technology
    • 1.5V to 3.3V I/O operation
    • Built-in ChipSync™ source-synchronous technology
    • Digitally controlled impedance (DCI) active termination
    • Fine grained I/O banking (configuration in one bank)
  • Flexible Logic Resources
  • Secure Chip AES Bitstream Encryption
  • 90 nm Copper CMOS Process
  • 1.2V Core Voltage
  • Flip-Chip Packaging including Pb-Free Package Choices

Technical Attributes

Find Similar Parts
Description Value
IC Mounting Surface Mount
IC Case / Package FCBGA
Operating Temperature Max 85
No. of User I/Os 640
No. of Pins 1148
No. of Logic Cells 55
Speed Grade 10

ECCN / UNSPSC / COO

Description Value
ECCN: 3A991.d
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Documents

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Documents

Title Download Type Date Published
Functional Description of the Virtex-4 FPGA Architecture User-Guides 20130331
Virtex-4 Family Overview Product-Guides 20130331
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