Manufacturer:
AMD
Product Category:
Programmable Logic,
IP Cores
EF-DI-TCCENC-LTE-SITE
The 3GPP LTE Turbo Encoder implements the turbo convolutional encoding scheme defined in the 3GPP LTE specifications. The 3GPP Turbo Encoder can be used in conjunction with the 3GPP LTE Turbo Decoder core.
Avnet Manufacturer Part #:
EF-DI-TCCENC-LTE-SITE
RoHS Non-Compliant
NCNR
The 3GPP LTE Turbo Encoder implements the turbo convolutional encoding scheme defined in the 3GPP LTE specifications. The 3GPP Turbo Encoder can be used in conjunction with the 3GPP LTE Turbo Decoder core.
Key Features
- Implements the turbo encoder as defined in 3GPP TS 36.212 v9.0.0 Multiplexing and Channel Coding specification.
- Core contains the full 3GPP LTE interleaver
- All 188 3GPP LTE block sizes (40
- 6144) supported
- FIFO-buffered symbol memory for maximum throughput
- Flexible interfacing using optional control signals
- For use with the Xilinx® Core Generator™ software v13.2
- Bit-accurate C model available.
Technical Attributes
Find Similar Parts|
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Description | Value |
|---|---|---|
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Supported FPGA Families | Zynq-7000|Artix-7|Ki |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| ECCN: | EAR99 |
| SCHEDULE B: | 8542310000 |
| HTSN: | 8542310001 |