AT45DB161E-SHD-B

The Adesto AT45DB161E is a 2.3V or 2.5V minimum, serial-interface sequential access Flash memory ideally suited fora wide variety of digital voice, image, program code, and data storage applications. The AT45DB161E also supports theRapidS serial interface for applications requiring very high speed operation. Its 17,301,504 bits of memory are organizedas 4,096 512 bytes or 528 bytes each. In addition to the main memory, the AT45DB161E also contains twoSRAM buffers of 512/528 bytes each. The buffers allow receiving of data while main memory is beingreprogrammed. Interleaving between both buffers can dramatically increase a system's ability to write a continuous datastream. In addition, the SRAM buffers can be used as additional system scratch pad memory, and E2PROM emulation(bit or byte alterability) can be easily handled with a self-contained three step read-modify-write operation.Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, theAdesto DataFlash uses a serial interface to sequentially access its data. The simple sequential access dramaticallyreduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise,and reduces package size. The device is optimized for use in many commercial and industrial applications wherehigh-density, low-pin count, low-voltage, and low-power are essential.To allow for simple in-system re-programmability, the AT45DB161E does not require high input voltages forprogramming. The device operates from a single 2.3V to 3.6V or 2.5V to 3.6V power supply for the erase and programand read operations. The AT45DB161E is enabled through the Chip Select pin (CS) and accessed via a 3-wire interfaceconsisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).All programming and erase cycles are self-timed.

• Single 2.3V - 3.6V or 2.5V - 3.6V supply
• Serial Peripheral Interface (SPI) compatible
• Supports SPI modes 0 and 3
• Supports RapidS™ operation
• Continuous read capability through entire array
• Up to 85MHz
• Low-power read option up to 15MHz
• Clock-to-output time (tV) of 6ns maximum
• User configurable page size
• 512 bytes per page
• 528 bytes per page (default)
• Page size can be factory pre-configured for 512 bytes
• Two fully independent SRAM data buffers (512/528 bytes)
• Allows receiving data while reprogramming the main memory array
• Flexible programming options
• Byte/Page Program (1 to 512/528 bytes) directly into main memory
• Buffer Write
• Buffer to Main Memory Page Program
• Flexible erase options
• Page Erase (512/528 bytes)
• Block Erase (4KB)
• Sector Erase (128KB)
• Chip Erase (16-Mbits)
• Program and Erase Suspend/Resu