MC14526BDWR2G
Presettable 4-Bit Down Counters. ONSSPCLGC;
The MC14526B binary counter is constructed with MOS P-channel and N-channel enhancement mode devices in a monolithic structure. This device is presettable, cascadable, synchronous down counter with a decoded "0"" state output for divide-by-N applications. In single stage applications the ""0"" output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide-by-N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock. This complementary MOS counter can be used in frequency synthesizers, phase-locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity."
- Supply Voltage Range = 3.0 Vdc to 18 Vdc
- Logic Edge-Clocked Design - Incremented on Positive Transition of Clock or Negative Transition of Inhibit
- Asynchronous Preset Enable
- Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range
- Pb-Free Packages are Available
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Uni-Directional | ||
| Matte Tin | ||
| 4000 | ||
| Counter/Divider | ||
| 260 | ||
| 1100@5V|450@10V|320@15V ns | ||
| 0.02 mA | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 0 | ||
| 4 | ||
| 4 | ||
| 1 | ||
| 0 | ||
| 4 | ||
| -55 to 125 °C | ||
| Down Counter | ||
| 16SOIC W | ||
| Yes | ||
| 16 | ||
| Asynchronous | ||
| 10.45 x 7.6 x 2.4 mm | ||
| 50 pF | ||
| No | ||
| Asynchronous | ||
| SOIC W | ||
| Yes | ||
| Positive-Edge/Negative-Edge | ||
| Binary | ||
| 3.3|5|9|12|15 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | null |
| ECCN: | EAR99 |
| HTSN: | PARTS... |
| Schedule B: | PARTS... |
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