HEF4013BT,653
Flip-Flop, HEF4013, D, 30 ns, 40 MHz, 2.4 mA, SOIC
- RoHS 10 Compliant
- Tariff Charges
The HEF4013BT is a Dual D-type Flip-flop features independent set-direct input (SD), clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is LOW and is transferred to the output on the positive-going edge of the clock. The active high asynchronous CD and SD inputs are independent and override the D or CP inputs. The outputs are buffered for best system performance. The clock input's Schmitt-trigger action makes the circuit highly tolerant of slower clock rise and fall times. It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.
- Tolerant of slow clock rise and fall times
- Fully static operation
- Standardized symmetrical output characteristics
- Complies with JEDEC standard JESD 13-B
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 0 | ||
| Single-Ended | ||
| Gold | ||
| HEF4000 | ||
| D-Type | ||
| 260 °C | ||
| -4.2 mA | ||
| 60@15V ns | ||
| 0.004 uA | ||
| 3 V | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 2 | ||
| 1 | ||
| 1 | ||
| 2 | ||
| 0 | ||
| -40 to 125 °C | ||
| Differential | ||
| 14SO | ||
| 14 | ||
| Inverting|Non-Inverting | ||
| 8.75 x 4 x 1.45 mm mm | ||
| 50 pF | ||
| No | ||
| Automotive | ||
| Set, Reset | ||
| SOIC | ||
| Positive-Edge | ||
| 5|10 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | null |
| ECCN: | EAR99 |
| HTSN: | 8542390001 |
| Schedule B: | 8542390000 |