74LV4053PW,118

The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All three switches share an enable input (E). A HIGH on E causes all switches into the high-impedance OFF-state, independent of Sn. VCC and GND are the supply voltage connections for the digital control inputs (Sn and E). The VCC to GND range is 1 V to 6 V. The analog inputs/outputs (nY0, nY1 and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC- VEE may not exceed 6 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground). VEE and VSS are the supply voltage connections for the switches.

• Optimized for low-voltage applications: 1.0 V to 3.6 V
• Accepts TTL input levels between V_CC = 2.7 V and V_CC = 3.6 V
• Low ON resistance:
  • 180 ? (typical) at V_CC - V_EE = 2.0 V
  • 100 ? (typical) at V_CC - V_EE = 3.0 V
  • 75 ? (typical) at V_CC - V_EE = 4.5 V
• Logic level translation:
  • To enable 3 V logic to communicate with ±3 V analog signals
• Typical ‘break before make’ built in
• ESD protection:
  • HBM JESD22-A114-C exceeds 2000 V
  • MM JESD22-A115-A exceeds 200 V
• Multiple package options
• Specified from -40 ? to +85 ? and from -40 ? to +125 ?