74HC4020D,653
Counter, Binary Ripple, 74HC, 109 MHz, Max Count 16383, 2 V to 6 V, 16 Pins, SOIC
The 74HC4020; 74HCT4020 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4020B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4020; 74HCT4020 are 14-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0, Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop.
- Multiple package options
- Complies with JEDEC standard no. 7A
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Uni-Directional | ||
| Gold | ||
| HC | ||
| Counter | ||
| 260 | ||
| 140@2V|28@4.5V|24@6V ns | ||
| 0.008 mA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 0 | ||
| 1 | ||
| 12 | ||
| 1 | ||
| 0 | ||
| 14 | ||
| -40 to 125 °C | ||
| UP Counter | ||
| 16SO | ||
| No | ||
| 16 | ||
| 10 x 4 x 1.45 mm | ||
| 50 pF | ||
| No | ||
| Asynchronous | ||
| SOIC | ||
| No | ||
| Negative-Edge | ||
| Binary | ||
| 5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | null |
| ECCN: | EAR99 |
| HTSN: | 8542390001 |
| Schedule B: | 8542390000 |
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