74AVCH2T45GS,115

The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (Vcc(A) and Vcc(B)). Both Vcc(A) and Vcc(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to Vcc(A) and pins nB are referenced to Vcc(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA. The device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either Vcc(A) or Vcc(B) are at GND level, both A and B are in the high-impedance OFF-state. The 74AVCH2T45 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

• Wide supply voltage range:
  • Vcc(A): 0.8 V to 3.6 V
  • Vcc(B): 0.8 V to 3.6 V
• High noise immunity
• Complies with JEDEC standards:
  • JESD8-12 (0.8 V to 1.3 V)
  • JESD8-11 (0.9 V to 1.65 V)
  • JESD8-7 (1.2 V to 1.95 V)
  • JESD8-5 (1.8 V to 2.7 V)
  • JESD8-B (2.7 V to 3.6 V)
• ESD protection:
  • HBM JESD22-A114F Class 3B exceeds 8000 V
  • MM JESD22-A115-A exceeds 200 V
  • CDM JESD22-C101C exceeds 1000 V
• Maximum data rates:
  • 500 Mbps (1.8 V to 3.3 V translation)
  • 320 Mbps (< 1.8 V to 3.3 V translation)
  • 320 Mbps (translate to 2.5 V or 1.8 V)
  • 280 Mbps (translate to 1.5 V)
  • 240 Mbps (translate to 1.2 V)
• Suspend mode
• Bus hold on data inputs
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 % of Vcc
• Ioff