74AHC594PW,118
Shift Register, 74AHC594, Serial to Parallel, Serial to Serial, 1 Element, 8 -Bit, 16 Pins, TSSOP
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RoHS 10 Compliant -
Tariff Charges
The 74AHC594PW is a 8-bit Si-gate CMOS Shift Register with output register. It is pin compatible with low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. This non-inverting serial-in parallel-out shift register feeds an 8-bit D-type storage register. Separate clocks (SHCP\ and STCP\) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes. Both the shift and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one count pulse ahead of the storage register.
- Balanced propagation delays
- All inputs have Schmitt-trigger actions
- Inputs accept voltages higher than VCC
- Independent direct overriding clears on shift and storage registers
- Independent clocks for shift and storage registers
- Latch-up performance exceeds 100mA per JESD78 class II
- CMOS Input level
- Complies with JEDEC standard No. 7A
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Uni-Directional | ||
| Gold over Nickel Palladium | ||
| AHC | ||
| Shift Register | ||
| 260 °C | ||
| 8@4.5V to 5.5V ns | ||
| 4 uA | ||
| Surface Mount | ||
| 1 | ||
| 0 | ||
| 1 | ||
| 9 | ||
| 1 | ||
| 0 | ||
| 8 | ||
| 2 to 5.5 V | ||
| -40 to 125 to 125 °C | ||
| Serial to Serial/Parallel | ||
| 16TSSOP | ||
| No | ||
| 16 | ||
| 5.1 x 4.5 x 0.95 mm | ||
| 50 pF | ||
| No | ||
| TSSOP | ||
| No | ||
| Positive-Edge | ||
| Octal | ||
| 5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | null |
| ECCN: | EAR99 |
| HTSN: | 8542390001 |
| Schedule B: | 8542390000 |
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