74AHC594BQ,115

The 74AHC594; 74AHCT594 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC594; 74AHCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes. Both the shift and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks tog

Balanced propagation delays ¦ All inputs have Schmitt-trigger actions ¦ Inputs accept voltages higher than VCC ¦ Wide supply voltage range from 2.0 V to 5.5 V ¦ 8-bit serial-in, parallel-out shift register with storage ¦ Independent direct overriding clears on shift and storage registers ¦ Independent clocks for shift and storage registers ¦ Latch-up performance exceeds 100 mA per JESD78 Class II ¦ Input levels: ? For 74AHC594: CMOS level ? For 74AHCT594: TTL level ¦ ESD protection: ? HBM EIA/JESD22-A114E exceeds 2000 V ? MM EIA/JESD22-A115-A exceeds 200 V ? CDM EIA/JESD22-C101C exceeds 1000 V ¦ Multiple package options ¦ Specified from -40 °C to +85 °C and from -40 °C to +125 °C