MT53E512M32D1ZW-046 WT:B
DRAM, Mobile LPDDR4, 16 Gbit, 512M x 32bit, 2.133 GHz, 200 Pins, TFBGA
MT53E512M32D1 is a 16Gb mobile low-power DDR4 SDRAM with low VDDQ (LPDDR4X) high-speed, CMOS dynamic random-access memory device. This device is internally configured with 2 channels or 1 channel ×16 I/O, each channel having 8-banks.
- 16n prefetch DDR architecture, 8 internal banks per channel for concurrent operation
- Single-data-rate CMD/ADR entry, bidirectional/differential data strobe per byte lane
- Programmable READ and WRITE latencies (RL/WL), programmable VSS (ODT) termination
- Directed per-bank refresh for concurrent bank operation and ease of command scheduling
- On-chip temperature sensor to control self refresh rate, partial-array self refresh (PASR)
- Selectable output drive strength (DS), clock-stop capability, single-ended CK and DQS support
- 1.10V VDD2 / 0.60V VDDQ or 1.10V VDDQ operating voltage
- 512 Meg x 32 configuration, LPDDR4, 1 die addressing
- 200-ball TFBGA (Ø0.40 SMD) package, 468ps cycle time
- Operating temperature rating range from -25°C to +85°C
Technical Attributes
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| Description | Value | |
|---|---|---|
| 2.133 GHz | ||
| Mobile LPDDR4 | ||
| TFBGA | ||
| Surface Mount | ||
| 512M x 32bit | ||
| 16 Gbit | ||
| 200 | ||
| 85 °C | ||
| -25 °C | ||
| 1.1 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | null |
| ECCN: | EAR99 |
| HTSN: | null |
| Schedule B: | null |
Factory Lead Time: