MT46H128M16LFDD-48 IT:C

MT46H128M16LFDD-48 IT:C 2Gb mobile low-power DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 2,147,483,648 bits. It is internally configured as a quad-bank DRAM. Each of the x16’s 536,870,912-bit banks is organized as 16,384 rows by 2048 columns by 16 bits. Each of the x32’s 536,870,912-bit banks is organized as 16,384 rows by 1024 columns by 32 bits.

• VDD/VDDQ = 1.70 - 1.95V, bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#), commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• 4 internal banks for concurrent operation, data masks (DM) for masking write data; one mask per byte
• Concurrent auto precharge option is supported, auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs, temperature-compensated self refresh (TCSR)²
• Partial-array self refresh, deep power-down, status read register (SRR), clock stop capability
• 64ms refresh; 32ms for the automotive temperature range, selectable output drive strength (DS)
• 60-ball VFBGA package, industrial operating temperature range from -40°C to +85°C